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| ICS503 LOCOTM PLL CLOCK MULTIPLIER Description The ICS503 is a member of the LOCOTM family, the most cost effective way to generate a high-quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 160 MHz. Stored in the chip's ROM is the ability to generate nine different multiplication factors, allowing one chip to output many common frequencies (see table on page 2). This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. For applications which require defined input to output skew, use the ICS570B. Features * Packaged as 8-pin SOIC or die * ICS' lowest cost PLL clock * Generates 16.9344 MHz for stereo codecs from the 14.31818 MHz motherboard clock. * Can be cost effective in replacing a single surface-mount crystal * * * * * * * * * Can be driven by other 5xx series Input crystal frequency of 5 - 27 MHz Input clock frequency of 2 - 50 MHz Output clock frequencies up to 160 MHz Low jitter - 50 ps one sigma Duty cycle of 45/55 up to 160 MHz Operating voltages of 3.0 to 5.5V 25 mA drive capability at TTL levels Advanced, low power CMOS process Block Diagram VDD S1, S0 X1/ICLK Crystal or Clock input X2 Optional crystal capacitors 2 CLK PLL Clock Multiplier Circuitry and ROM Crystal OScillator GND MDS 503 B I n t e gra te d C i r c u i t S y s t e m s 1 5 25 Race Stre et, San Jo se, CA 9 5126 Revision 031504 te l (40 8) 2 97-12 01 w w w. i c st . c o m ICS503 LOCOTM PLL Clock Multiplier Pin Assignment X1/ I CLK VDD GND REF 1 2 3 4 8 7 6 5 X2 S1 S0 CLK 8 - p i n ( 1 5 0 mi l ) S OI C Clock Decoding Table (MHz) S1 S0 0 0 0 M M M 1 1 1 0 M 1 0 M 1 0 M 1 Multiplier 10 16 1.1111 2.4444 2.4164 2.4 5.5873 1.1827 4.1905 Typ. Input (MHz) 10 10 27 14.31818 14.31818 14.31818 14.31818 14.31818 14.31818 CLK (MHz) 100 160 30 35 34.60 34.36 80 16.934 60 Input Range (MHz) at 5.0 V 2 < Input < 16 2 < Input < 10 20 < Input < 50 10 < Input < 50 10 < Input < 50 10 < Input < 50 14 < Input < 28 14 < Input < 30 5 < Input < 38 Input Range (MHz) at 3.3 V 2 < Input < 16 2 < Input < 6 20 < Input < 40 10 < Input < 40 10 < Input < 40 10 < Input < 40 14 < Input < 18 14 < Input < 30 5 < Input < 24 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) MDS 503 B In te grated Circuit Systems 2 525 Ra ce Street, San Jose, CA 9512 6 Revision 031504 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS503 LOCOTM PLL Clock Multiplier Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name XI/ICLK VDD GND NC CLK S0 S1 X2 Pin Type Input Power Power -- Output Tri-level Input Tri-level Input Output Pin Description Crystal connection or clock input. Connect to +3.3 V or +5 V. Connect to ground. No connect. Do not connect anything to this pin. Clock output per table above. Output frequency equals input freuency times multiplier. Select 0 for output clock. Connect to GND or VDD or float. Select 1 for output clock. Connect to GND or VDD or float. Crystal connection. Leave unconnected for clock input. MDS 503 B In te grated Circuit Systems 3 525 Ra ce Street, San Jose, CA 9512 6 Revision 031504 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS503 LOCOTM PLL Clock Multiplier External Components Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS503 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and GND. It must be connected close to the ICS503 to minimize lead inductance. No external power supply filtering is required for the ICS503. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -12 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2] = 8. Series Termination Resistor A 33 terminating resistor can be used next to the CLK pin. The total on-chip capacitance is approximately 12 pF. A parallel resonant, fundamental mode crystal should be used. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS503. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 260C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +3 Typ. - Max. +70 +5.5 Units C V MDS 503 B In te grated Circuit Systems 4 525 Ra ce Street, San Jose, CA 9512 6 Revision 031504 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS503 LOCOTM PLL Clock Multiplier DC Electrical Characteristics VDD=5.0 V 5% , Ambient temperature 0 to +70C, unless stated otherwise Parameter Operating Voltage Input High Voltage, ICLK only Input Low Voltage, ICLK only Input High Voltage Input Mid Voltage Input Low Voltage Output High Voltage, CMOS high Output High Voltage, CMOS high Output Low Voltage IDD Operating Supply Current, 14 MHz crystal Short Circuit Current Input Capacitance, S1, S0 Symbol VDD VIH VIL VIH VIM VIL VOH VOH VOL Conditions ICLK (pin 1) ICLK (pin 1) S0, S1 S1, S0 S0, S1 IOH = -4 mA IOH = -25 mA IOL = 25 mA No load, 80 MHz CLK output Pins 6, 7 Min. 3 Typ. Max. 5.5 Units V V V V V (VDD/2)+1 VDD/2 VDD/2 VDD-0.5 VDD/2 0.5 VDD-0.4 2.4 0.4 16 +70 4 (VDD/2)-1 V V V V mA mA pF AC Electrical Characteristics VDD = 5.0V 5%, Ambient Temperature 0 to +70 C, unless stated otherwise Parameter Input Frequency, crystal input Input Frequency, clock input Output Frequency, VDD = 4.5 to 5.5V Output Frequency, VDD = 3.0 to 3.6V Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Absolute Clock Period Jitter One Sigma Clock Period Jitter tOR tOF tOD tja tjs 0.8 to 2.0 V 2.0 to 8.0V at VDD/2 Deviation from mean 45 Symbol FIN FIN FOUT Conditions Min. 5 2 14 14 Typ. Max. 27 50 160 100 Units MHz MHz MHz MHz ns ns 1 1 49-51 +100 30 55 % ps ps MDS 503 B In te grated Circuit Systems 5 525 Ra ce Street, San Jose, CA 9512 6 Revision 031504 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS503 LOCOTM PLL Clock Multiplier Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Symbol Millimeters Min Max Inches Min Max Index Area EH Pin 1 A A1 B C D E e H h L a h x 45 0 1.35 1.75 1.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 Basic 5.80 6.20 0.25 0.50 0.40 1.27 0 8 0.0532 0.0688 0.0040 0.0098 0.013 0.020 0.0075 0.0098 .1890 .1968 0.1497 0.1574 0.050 Basic 0.2284 0.2440 0.010 0.020 0.016 0.050 0 8 D A Q e b c Ordering Information Part / Order Number (Note 1) ICS503M ICS503MT Marking ICS501M ICS501M Shipping packaging Tubes Tape and Reel Package 8 pin SOIC 8 pin SOIC Temperature 0 to +70 C 0 to +70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 503 B In te grated Circuit Systems 6 525 Ra ce Street, San Jose, CA 9512 6 Revision 031504 tel (4 08) 297 -1 201 w w w. i c s t . c o m |
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